In typical prior art computer systems, a processor may access data from memory by first checking to see whether a valid copy of the requested data exists within a cache, such as a level one (L1) cache. In order to determine whether a valid copy of the requested data is present within a cache line, the processor will typically perform a special operation, such as a snoop operation, to check the validity of a line of cache corresponding to a particular address. If the snoop returns a favorable result (e.g.,. a cache “hit”), the processor may then access the desired data from the line of cache memory. However, if the snoop results in an unfavorable result (e.g., a cache “miss”), the processor may have to resort to another memory source, such as main system memory, for the desired data.
In the either case, the snoop cycle may result in latency, because it is an extra operation that must be performed before accessing the desired data. FIG. 1 illustrates a prior art computer system in which a microprocessor, or processor core, accesses a cache that is internal or external to the processor package. The processor accesses the cache by addressing a cache line on the address lines, address[31:0]. A snoop operation first determines whether a valid copy of the desired data exists at the addressed cache line. If a valid copy of the data does exist, the data is then accessed by the processor via a read operation, which returns the requested data to the processor on the data lines, data[63:0]. However, if a valid copy of the desired data does not exist at the addressed location within the cache, the processor may have to access other memory, such as dynamic random access memory (DRAM), which may have slower access speeds, thereby resulting in even more computer system latency.